The present invention relates generally to the provision of low-K (reduced from 4.0 to approximately 3.3) gate sidewall spacers by fluorine implantation in a MOSFET device, and more particularly pertains to a MOSFET structure, and a method of fabrication thereof, having fluorine doped gate oxide sidewall spacers, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs
Device feature scaling has associated fundamental problems which tend to degrade overall power dissipation including:
increased stud or via capacitance as a result of sidewall spacer thickness reduction;
increased overlap capacitance as a result of gate dielectric thickness scaling;
increased GIDL (gate-induced drain leakage) current as a result of a thinner gate dielectric in the gate-to-diffusion overlap region;
degraded dielectric breakdown at the gate edge.